1. Field of the Invention
The present invention relates generally to integrated circuits, and more particularly to under bump metallization pads and solder bumps on a die for flip chip type attachment to a printed circuit board or the like.
2. Description of the Related Art
Solder ball or bump technology is commonly used for electrical and mechanical interconnection of an integrated circuit to a substrate. High performance microelectronic devices may comprise a number of flip chips, i.e., a chip or die that has a pattern or array of terminations spaced around the active surface of the die for face-down mounting of the die to a substrate, having a Ball Grid Array (BGA) or a Slightly Larger than Integrated Circuit Carrier (SLICC). Each flip chip may be attached to a ceramic or silicon substrate or printed circuit board (PCB), such as an FR-4 board, for electrical interconnection to other microelectronic devices. For example, a very large scale integration (VLSI) chip may be electrically connected to a substrate, printed circuit board, or other next higher level packaging carrier member using solder balls or solder bumps. This connection technology may be referred to generically as “flip chip” or “Controlled Collapse Chip Connection (C4)” attachment.
Flip chip attachment requires the formation of contact terminals at flip chip contact sites on the semiconductor die, each site having a metal pad with a lead/tin solder ball formed thereon. Flip chip attachment also requires the formation of solder joinable sites (“pads”) on the metal conductors of the PCB or other substrate or carrier which are a mirror-image of the solder ball arrangement on the flip chip. The pads on the substrate are usually surrounded by non-solderable barriers so that when the solder balls of the chip contact sites aligned with the substrate pads and are “reflowed,” the surface tension of the liquified solder element supports the semiconductor chip above the substrate. After cooling, the chip is essentially soldered face-down by very small, closely spaced, solidified solder interconnections. An underfill encapsulant is generally disposed between the semiconductor die and the substrate for environmental protection, and to further enhance the mechanical attachment of the die to the substrate.
FIGS. 1a–1h show a known method of forming a conductive ball arrangement on a flip chip. First, a plurality of semiconductor elements such as dice including integrated circuitry (not shown) are fabricated on a face surface 12 of a semiconductor wafer 10. A plurality of conductive traces 14 are formed on the semiconductor wafer surface 12 in a position to contact circuitry of the respective semiconductor elements (not shown), as shown in FIG. 1a. A passivation film 16, such as at least one layer of SiO2 film, Si3N4 film, or the like is formed over the semiconductor wafer surface 12 as well as the conductive traces 14 as shown in FIG. 1b. A first layer of etchant-resistive photoresist film 18 is then applied to a face surface 20 of the passivation film 16. The first photoresist film 18 is then masked, exposed, and stripped to form the desired openings (one illustrated) in the first photoresist film 18. The passivation film 16 is then etched through the opening in photoresist film 18 to form a via 22 with either sloped edges or walls 26 or straight (vertical) walls if desired, and which exposes a face surface 24 of the conductive trace 14, as shown in FIG. 1c. Photoresist 18 is then stripped, as shown in FIG. 1d. 
FIG. 1e shows metal layers 28, 30, and 32 applied over the passivation film face surface 20 as well as the via 22 to form a multi-layer under bump metallurgy (UBM) 34 by chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or physical vapor deposition (PVD) (sputtering or evaporation). The metal layers usually comprise chromium for the first or base adhesion layer 28, chromium-copper alloy for a second, intermediate layer 30, and copper for the third, outer soldering layer 32. Additionally, a fourth metal layer (not shown) of flashed gold may be placed atop the copper third layer 32 to prevent oxidation of the copper. Nickel, palladium and platinum have also been employed as the outer or soldering layer 32. Furthermore, titanium or titanium/tungsten alloys have been used as alternatives to chromium for the adhesion layer. Two-layer UBMs with a gold flash coating are also known, as are single-layer UBMs.
A second layer of etchant-resistive photoresist film 35 is applied to a face surface 38 of the third metal layer 32. The second photoresist film 35 is then masked, exposed, and stripped to form at least one second etchant-resistive block 36 over the via 22, as shown in FIG. 1f. The metal layers 28, 30, and 32 surrounding the via 22 are then etched and the etchant-resistive block 36 is stripped to form a discrete UBM pad 40, as shown in FIG. 1g. A solder bump 42 is then formed on the UBM pad 40, as shown in FIG. 1h, by any known industry technique, such as stenciling, screen printing, electroplating, electroless plating, evaporation or the like.
The UBM pads 40 can also be made by selectively depositing the metal layers by evaporation through a mask (or photoengraving) onto the passivation film face surface 20 as well as the via 22 such that the metal layers 28, 30, and 32 correspond to the exposed portions of the conductive traces 14.
Solder balls are generally formed of lead and tin. High concentrations of lead are sometimes used to make the bump more compatible with subsequent processing steps. Tin is added to strengthen bonding (to such metal as copper) and serves as an antioxidant. High temperature (melting point approximately 315° C.) solder alloy has been used to join chips to thick ceramic substrates and multi-layer cofired ceramic interface modules. Joining chips to organic carriers such as polymide-glass, polyimide-aramid and the like as well as the printed wiring boards requires lower temperatures which may be obtained by using 63 In/37 Pb solder (melting point approximately 183° C.) and various Pb/In alloys such as 50 Pb/50 In (melting point approximately 220° C.). Lower melting point alloys (down to 60° C.) have been used to bump very temperature-sensitive chips such as GaAs and superconducting Josephson junctions.
Numerous techniques have been devised to improve the formation of UBM and solder bumps for flip chips. For example, U.S. Pat. No. 4,360,142 issued Nov. 23, 1982 to Carpenter et al. relates to forming multiple layer UBM pads between a semiconductor device and a supporting substrate particularly suited to high stress use conditions that generate thermal gradients in the interconnection.
U.S. Pat. No. 5,137,845 issued Aug. 11, 1992 to Lochon et al. pertains to a method of forming solder bumps and UBM pads of a desired size on semiconductor chips based on an involved photolithographic technique such that the dimensions of the solder bumps can be reduced in order to increase the number of bumps on a chip.
U.S. Pat. No. 5,470,787 issued Nov. 28, 1995 to Greer relates to a substantially cylindrical layered solder bump wherein the bump comprises a lower tin layer adjacent to the UBM pad, a thick lead layer, and an upper tin layer to provide an optimized, localized eutectic formation at the top of the bump during solder reflux.
U.S. Pat. Nos. 5,293,006 and 5,480,835 also dislcose materials and techniques for forming UBM pads and solder bumps.
There are problems, however, with the conventional techniques for forming UBM pads and solder bumps. All of the above patents and prior art techniques for forming UBM pads and solder bumps are relatively complex and require a substantial number of discrete steps to form the flip chip conductive bumps.
Thus, there exists a need for more efficient conductive bump structures on a flip chip to eliminate some of the steps required by present industry standard techniques while using commercially-available, widely-practiced semiconductor device fabrication materials and techniques.